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Trusted Irix /B 4.0.4
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mp_gio.h.z
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mp_gio.h
Wrap
C/C++ Source or Header
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1992-04-03
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5KB
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146 lines
#ifndef __SYS_MP_GIO_H__
#define __SYS_MP_GIO_H__
/*
* $Revision: 1.12 $
*
* Description of address spaces for the MP bus to GIO bus adapter.
*
* All the local registers of the MP_GIO adapter are mapped to MP
* slot 0xc.
*
*/
#define MG1_REGISTERS_SIZE 0x1000 /* 1 page of adapter registers */
#define MG1_3WAY_CMD_MAPPER_SIZE 0x20000 /* 128Kb or 32Kwords */
#define MG1_PROM_SIZE 0x80000 /* 128 pages with each word containing only one valid byte*/
#define GIO_SIZE 0x400000 /* 4Mb GIO space */
#define IP17_3WAY_SIZE 0x2000 /* 2 pages */
/*
* Adapter control register 1 bit masks.
*/
#define MG1_CTL1_DUALHD (0x1<<0) /* set to 1 for head 1, 0 for head 0 */
#define MG1_CTL1_FIFO_RDISABLE (0x1<<1) /* Fifo read disable */
#define MG1_CTL1_CMDMAP_ACCESS (0x1<<2) /* Command Mapper Access mode */
#define MG1_CTL1_RST_GIO (0x1<<3) /* 0 to reset GIO bus */
#define MG1_CTL1_RST_ADP (0x1<<4) /* 0 to reset adapter */
#define MG1_CTL1_DIAG_MODE (0x1<<5) /* diag mode bit */
#define MG1_CTL1_FIFO_CTL (0x1<<6) /* fifo control (set to 1 slight before, during, and slight after reset) */
#define MG1_CTL1_NOT_YET_DEF (0x1<<7)
#define MG1_CTL1_FAF_IE (0x1<<8) /* fifo almost full interrupt enable */
#define MG1_CTL1_VRI_IE (0x1<<9) /* vertical retrace interrupt enable */
#define MG1_CTL1_GFX_IE (0x1<<10) /* GFX interrupt enable */
#define MG1_CTL1_VII_IE (0x1<<11) /* Video interrupt enable */
#define MG1_CTL1_VSTAT_IE (0x1<<12) /* GFX Vstat interrupt enable */
#define MG1_CTL1_LE (0x1<<13) /* 1 for little endian host */
#define MG1_CTL1_DBL_R (0x1<<14) /* Double word read PIO */
#define MG1_CTL1_ADPFIFO_BYP (0x1<<15) /* 1 to bypass adapter fifo */
/*
* Adapter control register 2 bit masks.
*/
#define MG1_CTL2_3WAY_B (0x1<<0) /* 3way type B */
#define MG1_CTL2_DIAG_STRT (0x1<<1) /* diagnostic start */
#define MG1_CTL2_DIAG0 (0x1<<2) /* diag command number 0 */
#define MG1_CTL2_DIAG1 (0x1<<3) /* diag command number 1 */
#define MG1_CTL2_STATIC_0_OFFSET (0x1<<4)
#define MG1_CTL2_STATIC_1_OFFSET (0x1<<5)
/*
* Adapter status register bit masks.
*/
#define MG1_STAT_GFXDLY (0x1<<0) /* Graphics delay */
#define MG1_STAT_FREQ (0x1<<1) /* 0 means 25MHz, 1 means 33Mhz GIO bus */
#define MG1_STAT_GIO_FF (0x1<<2) /* GIO fifo full */
#define MG1_STAT_GIO_VRI (0x1<<3) /* GIO vert retrace interrupt */
#define MG1_STAT_GIO_VII (0x1<<4) /* GIO video interrupt */
#define MG1_STAT_GIO_GEI (0x1<<5) /* GIO GE interrupt */
#define MG1_STAT_GIO_VSTAT (0x1<<6) /* GIO VSTAT */
#define MG1_STAT_VVF (0x1<<7) /* Video VField */
#define MG1_STAT_DMASYNC (0x1<<8) /* GFX DMA sync */
#define MG1_STAT_ADP_FF (0x1<<9) /* Adapter fifo full (active hi)*/
/* bit 10 unused currently */
#define MG1_STAT_ADP_FAF (0x1<<11) /* Adapter fifo almost full (active hi)*/
#define MG1_STAT_ADP_FAE (0x1<<12) /* Adapter fifo almost empty (active hi)*/
#define MG1_STAT_ADP_FE (0x1<<13) /* Adapter fifo empty (active low)*/
#define MG1_STAT_DIAG_DONE (0x1<<14) /* diag complete */
#define MG1_STAT_WRBYP_DONE (0x1<<15)
#ifdef LANGUAGE_C
struct mg1_regs {
volatile unsigned long id; /* ID register */
volatile unsigned long status; /* Status register */
volatile unsigned long control1; /* Control register 1*/
volatile unsigned long control2; /* Control register 2*/
volatile unsigned long upperGIOaddr; /* Upper GIO address */
volatile unsigned long fifo_control; /* fifo control register */
};
#endif /* LANGUAGE_C */
#ifdef _KERNEL
/* physical addresses of various MG1 hardware */
#define MG1_REGISTERS 0x17000000 /* Beginning of adapter registers */
#define MG1_3WAY_CMD_MAPPER 0x17020000 /* to 0x1703ffff */
#define MG1_PROM 0x17200000 /* Read only */
/* physical addresses of local registers */
#define MG1_ID 0x17000000 /* Read only */
#define MG1_STATUS 0x17000004 /* Read only */
#define MG1_CONTROL1 0x17000008 /* RW */
#define MG1_CONTROL2 0x1700000c /* RW */
#define MG1_UPPER_GIO 0x17000010 /* RW */
#define MG1_FIFO_CTL 0x17000014 /* RW */
/*
* macro that converts GIO physical addresses into
* MP bus addresses.
*/
#define GIO_TO_MP(x) (((x) - 0x1f000000) + 0x16400000) /* GIO address is mapped to MP slot 9 */
/* Wait for adapter fifo empty (bit set), and gfxdly deasserted (bit cleared) */
#define MG1WAIT \
{ \
int i = 0; \
while ( ((*(volatile long *)(PHYS_TO_K1(MG1_STATUS)) & \
(MG1_STAT_ADP_FE | MG1_STAT_GFXDLY)) != (MG1_STAT_ADP_FE)) \
&& (i++<1000000)); \
while ( ((*(volatile long *)(PHYS_TO_K1(MG1_STATUS)) & \
(MG1_STAT_ADP_FE | MG1_STAT_GFXDLY)) != (MG1_STAT_ADP_FE)) \
&& (i++<1000000)); \
if (i >= 1000000) \
dprintf("MG1WAIT: mg1 status reg:0x%x\n",*(volatile long *)(PHYS_TO_K1(MG1_STATUS))); \
}
#define GFXDLYWAIT \
{ \
int i = 0; \
while ( ((*(volatile long *)(PHYS_TO_K1(MG1_STATUS)) & \
(MG1_STAT_GFXDLY)) != 0) && (i++<1000000)); \
if (i >= 1000000) \
dprintf("GFXDLYWAIT: mg1 status reg:0x%x\n",*(volatile long *)(PHYS_TO_K1(MG1_STATUS))); \
}
#define BYPASS_WAIT(bd) \
{ \
int i = 0; \
while ((((struct mg1_regs *)(bd->adapter_base))->status & MG1_STAT_WRBYP_DONE) && (i++<1000000 )); \
if (i >= 1000000) \
dprintf("BYPASS_WAIT: mg1 status reg:0x%x\n",*(volatile long *)(PHYS_TO_K1(MG1_STATUS))); \
}
#endif /* _KERNEL */
#endif /* __SYS_MP_GIO_H__ */